This is an old revision of the document!
Table of Contents
JTAG is a technology to test integrated circuits, mostly micro-controllers and CPUs.
It allows to do hardware debugging: read/write memory, control I/Os, and debug running code.
SWD is a more modern version of JTAG and only requires 2 pins instead of 4[+1].
SWJ is a combination of Serial Wire Debug (SWD) and JTAG.
But they provide the same logical functions.
On one side this functionality must be included in the target device. The Debug Port is often called JTAG-DP for JTAG and SW-DP for SWD. SWJ capable device include and often combine both, as the SWD signal pins SWDIO and SWCLK re-use the JTAG signal pin JTMS and JTCK (backwards compatible).
Most 32 bits micro-controllers and SoCs have one of both (or both).
On the other side you need a SWJ adapter so the host can speak to the device using the JTAG and/or SWD protocol.
SWJ adapters can go from cheap (<5$) to expensive (>1000$), depending on the quality of the hardware and software.
SWJ adapters
These are the main SWJ adapters I am using.
ST-Link v2
The ST-LINK/V2 is from STMicroelectronics, and is very convenient to flash their STM8 and STM32 micro-controllers, such as the STM32 F1 series. It supports JTAG, SWD, and SWIM (for STM8).
These SWJ adapters are based STM32F1xx ARM Cortex M3 micro-controllers. And ironically enough I in turn use them to program and debug STM32F1xx ARM Cortex M3 micro-controllers.
First add the rules for normal users to be able to access the device (udev rule based on the VID and PID shown by lsusb). This has only to be done once, before the device is plugged in to be used:
echo -n 'ST-Link V2 SWJ adapter' | sudo tee -a /etc/udev/rules.d/60-st-linkv2.rules echo -n 'ATTR{idVendor}=="0483", ATTR{idProduct}=="3748", MODE="0666"' | sudo tee -a /etc/udev/rules.d/60-st-linkv2.rules sudo udevadm control --reload-rules
To connect to STM32F1xx ARM Cortex M3 micro-controllers I use OpenOCD:
openocd --file interface/stlink-v2.cfg --file target/stm32f1x.cfg Open On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-10:52) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'. Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD adapter speed: 1000 kHz adapter_nsrst_delay: 100 none separate Info : Unable to match requested speed 1000 kHz, using 950 kHz Info : Unable to match requested speed 1000 kHz, using 950 kHz Info : clock speed 950 kHz Info : STLINK v2 JTAG v17 API v2 SWIM v4 VID 0x0483 PID 0x3748 Info : using stlink api v2 Info : Target voltage: 3.534945 Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
I am using cheap clones.
BAITE
The first clone is a BAITE ST-Link V2. It supports JTAG, SWD, and SWIM (for STM8).
STM32F103C8 connection:
| STM32F103C8 signal | STM32F103C8 pin | adapter pin | adapter signal |
|---|---|---|---|
| PA7 | 17 | 1 | JRST |
| AMS1117 | 2 | 3V3 | |
| USB VCC | 3 | 5V | |
| PA4 | 14 | 4 | JTCK/SWCLK |
| PB11 | 22 | 5 | SWIM |
| PA14 | 37 | 6 | JTMS/SWDIO |
| USB GND | 7 | GND | |
| PA5 | 15 | 8 | JTDO |
| PB6 | 42 | 9 | SWIM_RST |
| PA6 | 16 | 10 | JTDI |
| PB12,PB14 | 25,27 | 100 ohms | |
| PB5 | 41 | LED |
the adapter pins are protected with a 220 ohms resistor.
aluminium
This one comes in aluminium case. It supports SWD, and SWIM (for STM8), but not JTAG. They replaced the additional JTAG pins with power pins.
STM32F103C8 connection:
| STM32F103C8 signal | STM32F103C8 pin | adapter pin | adapter signal |
|---|---|---|---|
| PB6 | 42 | 1 | RST |
| PB14 | 27 | 2 | SWDIO |
| USB GND | 3 | GND | |
| USB GND | 4 | GND | |
| PB8/PB11 | 45/22 | 5 | SWIM |
| PA5/PB13 | 15/26 | 6 | SWCLK |
| LDO VCC | 7 | 3.3V | |
| LDO VCC | 8 | 3.3V | |
| USB VCC | 9 | 5V | |
| USB VCC | 10 | 5V | |
| PA9 | 30 | current source | LED |
Altera USB-Blaster
The USB-Blaster is from Altera. It is often used to flash FPGA, but is a general purpose JTAG adapter.
I have a cheap Rev.c clone. The original uses FTDI FT245 and MAX CPLD chips. This one uses a Silicon Labs C8051F321 micro-controller and a 74LVC125 quad buffer, but there are many other clone variants.
be aware that here the VCC{TARGET} pin has to be connected to a reference voltage used for the JTAG communication, generally provided by the target device on the board (often 3.3V or 1.8V).
Else the signals can not be detected by the JTAG adapter.
First add the rules for normal users to be able to access the device (udev rule based on the VID and PID shown by lsusb). This has only to be done once, before the device is plugged in to be used:
echo -n 'Altera USB-Blaster JTAG adatper' | sudo tee -a /etc/udev/rules.d/60-altera-usb-blaster.rules echo -n 'ATTR{idVendor}=="09fb", ATTR{idProduct}=="6001", MODE="666"' | sudo tee -a /etc/udev/rules.d/60-altera-usb-blaster.rules sudo udevadm control --reload-rules
To be able to use it I had to recompile OpenOCD for the USB-Blaster to use libftdi (probable because it's a clone).
git clone http://git.code.sf.net/p/openocd/code openocd-code cd openocd-code ./bootstrap ./configure --enable-usb_blaster_libftdi make sudo make install cd ..
Else OpenOCD hangs, uses 100% CPU, and has to be killed using -KILL.
openocd --file interface/altera-usb-blaster.cfg Open On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-11:26) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only Info : only one transport option; autoselect 'jtag' adapter speed: 1000 kHz adapter_nsrst_delay: 100 jtag_ntrst_delay: 100 none separate cortex_m reset_config sysresetreq Info : No lowlevel driver configured, will try them all Info : Altera USB-Blaster II found (Firm. rev. = 6��) Info : This adapter doesn't support configurable speed
openocd --debug 3 --file interface/altera-usb-blaster.cfg ... Debug: 385 845 tcl.c:497 handle_nand_init_command(): Initializing NAND devices... Debug: 386 845 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_pld init Debug: 387 845 command.c:145 script_debug(): command - ocd_pld ocd_pld init Debug: 389 846 pld.c:207 handle_pld_init_command(): Initializing PLDs...
Now you can also use it, here with an STM32F1 micro-controller:
openocd --file interface/altera-usb-blaster.cfg --file target/stm32f1x.cfg Open On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-16:26) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only Info : only one transport option; autoselect 'jtag' adapter speed: 1000 kHz adapter_nsrst_delay: 100 jtag_ntrst_delay: 100 none separate cortex_m reset_config sysresetreq Info : No lowlevel driver configured, will try them all Info : usb blaster interface using libftdi Error: unable to get latency timer Info : This adapter doesn't support configurable speed Info : JTAG tap: stm32f1x.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3) Info : JTAG tap: stm32f1x.bs tap/device found: 0x16410041 (mfg: 0x020, part: 0x6410, ver: 0x1) Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
SEGGER J-Link
The O-Link-ARM V8 is a SEGGER J-Link clone.
It supports JTAG, SWD, SWO, RTCK, and voltage reference. That makes it the most complete JTAG adapter I have.
tricks
scan chain
JTAG devices are called Test Access Points (TAP). One micro-controller can have several TAPs, by chaining them. Devices with TAPs can also be chaining. But each TAP has an identity (IDCODE) and can be selected individually.
Thus it sometimes is useful to just list the TAPs available on a chain to know which devices are present.
This is easily done with urJTAG (here with the USB Blaster):
jtag UrJTAG 0.10 #2007 Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG. warning: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help. jtag> cable UsbBlaster Connected to libftdi driver. jtag> detect IR length: 9 Chain length: 2 Device Id: 00111011101000000000010001110111 (0x3BA00477) Unknown manufacturer! (01000111011) (/usr/share/urjtag/MANUFACTURERS) Device Id: 00010110010000010000000001000001 (0x16410041) Unknown manufacturer! (00000100000) (/usr/share/urjtag/MANUFACTURERS)
OpenOCD also scans the chain if no target is provided (the adapter still need to be defined):
openocd --file interface/altera-usb-blaster.cfg Open On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-16:26) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only Info : only one transport option; autoselect 'jtag' Info : No lowlevel driver configured, will try them all Info : usb blaster interface using libftdi Error: unable to get latency timer Info : This adapter doesn't support configurable speed Warn : There are no enabled taps. AUTO PROBING MIGHT NOT WORK!! Info : JTAG tap: auto0.tap tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3) Info : JTAG tap: auto1.tap tap/device found: 0x16410041 (mfg: 0x020, part: 0x6410, ver: 0x1) Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 4 -expected-id 0x3ba00477" Warn : AUTO auto1.tap - use "jtag newtap auto1 tap -irlen 5 -expected-id 0x16410041" Warn : gdb services need one or more targets defined
0x3ba00477 corresponds to the Cortex-M3 TAP, and 0x16410041 to the boundary scan TAP, as documented in the STM32F1xx reference manual.
While the ST-Link v2 is mainly meant to be used as SWD adapter, it also supports JTAG. Both are implemented with the High Level Adapter (HLA) driver. But it seems scan chain is not supported by the HLA.
openocd --file interface/stlink-v2.cfg -c "transport select hla_jtag" -c "adapter_khz 100" Open On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-16:26) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html hla_jtag adapter speed: 100 kHz Info : clock speed 100 kHz Error: BUG: current_target out of bounds