CuVoodoo STM32F1 firmware template
i2c_master.c
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1 /* This program is free software: you can redistribute it and/or modify
2  * it under the terms of the GNU General Public License as published by
3  * the Free Software Foundation, either version 3 of the License, or
4  * (at your option) any later version.
5  *
6  * This program is distributed in the hope that it will be useful,
7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9  * GNU General Public License for more details.
10  *
11  * You should have received a copy of the GNU General Public License
12  * along with this program. If not, see <http://www.gnu.org/licenses/>.
13  *
14  */
22 /* standard libraries */
23 #include <stdint.h> // standard integer types
24 #include <stdio.h> // standard I/O facilities
25 #include <stdlib.h> // general utilities
26 
27 /* STM32 (including CM3) libraries */
28 #include <libopencm3/stm32/rcc.h> // real-time control clock library
29 #include <libopencm3/stm32/gpio.h> // general purpose input output library
30 #include <libopencm3/stm32/i2c.h> // I2C library
31 #include <libopencm3/stm32/timer.h> // timer utilities
32 
33 #include "global.h" // global utilities
34 #include "i2c_master.h" // I2C header and definitions
35 
39 #define I2C_MASTER_I2C 2
45 #define I2C_MASTER_TIMER 4
46 #define I2C_MASTER_TIMEOUT 4
50 void i2c_master_setup(bool fast)
51 {
52  // configure I2C peripheral
53  rcc_periph_clock_enable(RCC_I2C_SCL_PORT(I2C_MASTER_I2C)); // enable clock for I2C I/O peripheral
54  gpio_set(I2C_SCL_PORT(I2C_MASTER_I2C), I2C_SCL_PIN(I2C_MASTER_I2C)); // already put signal high to avoid small pulse
55  gpio_set_mode(I2C_SCL_PORT(I2C_MASTER_I2C), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, I2C_SCL_PIN(I2C_MASTER_I2C)); // setup I2C I/O pins
56  rcc_periph_clock_enable(RCC_I2C_SCL_PORT(I2C_MASTER_I2C)); // enable clock for I2C I/O peripheral
57  gpio_set(I2C_SDA_PORT(I2C_MASTER_I2C), I2C_SDA_PIN(I2C_MASTER_I2C)); // already put signal high to avoid small pulse
58  gpio_set_mode(I2C_SDA_PORT(I2C_MASTER_I2C), GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, I2C_SDA_PIN(I2C_MASTER_I2C)); // setup I2C I/O pins
59  rcc_periph_clock_enable(RCC_AFIO); // enable clock for alternate function
60  rcc_periph_clock_enable(RCC_I2C(I2C_MASTER_I2C)); // enable clock for I2C peripheral
61  i2c_reset(I2C(I2C_MASTER_I2C)); // reset configuration
62  i2c_peripheral_disable(I2C(I2C_MASTER_I2C)); // I2C needs to be disable to be configured
63  i2c_set_clock_frequency(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/1000000); // configure the peripheral clock to the APB1 freq (where it is connected to)
64  if (fast) {
65  i2c_set_fast_mode(I2C(I2C_MASTER_I2C));
66  i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/(400000*2)); // set Thigh/Tlow to generate frequency of 400 kHz
67  i2c_set_trise(I2C(I2C_MASTER_I2C), (300/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 300 kHz is 300 ns
68  } else {
69  i2c_set_standard_mode(I2C(I2C_MASTER_I2C)); // the DS1307 has a maximum I2C SCL freq if 100 kHz (corresponding to the standard mode)
70  i2c_set_ccr(I2C(I2C_MASTER_I2C), rcc_apb1_frequency/(100000*2)); // set Thigh/Tlow to generate frequency of 100 kHz
71  i2c_set_trise(I2C(I2C_MASTER_I2C), (1000/(1000/(rcc_apb1_frequency/1000000)))+1); // max rise time for 100 kHz is 1000 ns (~1 MHz)
72  }
73  i2c_peripheral_enable(I2C(I2C_MASTER_I2C)); // enable I2C after configuration completed
74 
75  // configure time for timeouts
76  rcc_periph_clock_enable(RCC_TIM(I2C_MASTER_TIMER)); // enable clock for timer block
77  timer_reset(TIM(I2C_MASTER_TIMER)); // reset timer state
78  timer_set_mode(TIM(I2C_MASTER_TIMER), TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); // set timer mode, use undivided timer clock, edge alignment (simple count), and count up
79  timer_one_shot_mode(TIM(I2C_MASTER_TIMER)); // stop counter after update event (we only need to one timeout and reset before next operation)
80  if (fast) {
81  timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/400000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
82  } else {
83  timer_set_prescaler(TIM(I2C_MASTER_TIMER), rcc_ahb_frequency/100000-1); // set the prescaler so one tick is also one I2C bit (used I2C frequency)
84  }
85  timer_set_period(TIM(I2C_MASTER_TIMER), I2C_MASTER_TIMEOUT*9); // use factor to wait for all 9 bits to be transmitted
86  timer_update_on_overflow(TIM(I2C_MASTER_TIMER)); // only use counter overflow as UEV source (use overflow as timeout)
87 
88  // wait one transaction for the signal to be stable (some slave have issues when an I2C transaction immediately follows)
89  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
90  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
91  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
92  while ( !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF));
93  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
94  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
95 }
96 
97 bool i2c_master_read(uint8_t slave, const uint8_t* address, size_t address_size, uint8_t* data, size_t data_size)
98 {
99  // sanity check
100  if (address==NULL || address_size==0 || data==NULL || data_size==0) { // input data is erroneous
101  return false;
102  }
103  if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
104  return false;
105  }
106  if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
107  return false;
108  }
109 
110  bool to_return = false; // return if read succeeded
111 
112  // send start condition
113  i2c_send_start(I2C(I2C_MASTER_I2C)); // send start condition to start transaction
114  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
115  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
116  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
117  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
118  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
119  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
120  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
121  goto error;
122  }
123  if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // verify if in master mode
124  goto error;
125  }
126 
127  // select slave
128  i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, I2C_WRITE); // select slave
129  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
130  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
131  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
132  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
133  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
134  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
135  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
136  goto error;
137  }
138  if (!((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
139  goto error;
140  }
141 
142  // send address
143  for (size_t i=0; i<address_size; i++) {
144  i2c_send_data(I2C(I2C_MASTER_I2C), address[i]); // send memory address we want to read
145  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
146  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
147  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
148  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
149  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
150  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
151  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
152  goto error;
153  }
154  }
155 
156  // switch to read mode
157  i2c_send_start(I2C(I2C_MASTER_I2C)); // send restart condition to switch from write to read mode
158  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
159  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
160  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
161  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
162  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
163  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
164  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
165  goto error;
166  }
167 
168  i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, I2C_READ); // select slave
169  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
170  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
171  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
172  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
173  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
174  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
175  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
176  goto error;
177  }
178  if ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA)) { // verify we are in read mode (and read SR2 to clear ADDR)
179  goto error;
180  }
181 
182  // read data
183  for (size_t i=0; i<data_size; i++) { // read bytes
184  if (i==data_size-1) { // prepare to sent NACK for last byte
185  i2c_disable_ack(I2C(I2C_MASTER_I2C)); // NACK received to stop slave transmission
186  i2c_send_stop(I2C(I2C_MASTER_I2C)); // send STOP after receiving byte
187  } else {
188  i2c_enable_ack(I2C(I2C_MASTER_I2C)); // ACK received byte to continue slave transmission
189  }
190  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
191  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
192  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
193  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_RxNE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been received
194  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
195  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
196  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
197  goto error;
198  }
199  data[i] = i2c_get_data(I2C(I2C_MASTER_I2C)); // read received byte
200  }
201  to_return = true;
202 
203 error:
204  i2c_send_stop(I2C(I2C_MASTER_I2C)); // send stop to release bus
205  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
206  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
207  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
208  while ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until bus released (non master mode)
209  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
210  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
211  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
212  }
213  return to_return;
214 }
215 
216 bool i2c_master_write(uint8_t slave, const uint8_t* address, size_t address_size, const uint8_t* data, size_t data_size)
217 {
218  // sanity check
219  if (address==NULL || address_size==0 || data==NULL || data_size==0) { // input data is erroneous
220  return false;
221  }
222  if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_BUSY) { // I2C device is busy
223  return false;
224  }
225  if (I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) { // I2C device is already in master mode
226  return false;
227  }
228 
229  bool to_return = false; // return if read succeeded
230 
231  // send start condition
232  i2c_send_start(I2C(I2C_MASTER_I2C)); // send start condition to start transaction
233 
234  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
235  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
236  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
237  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_SB) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until start condition is transmitted
238  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
239  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
240  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
241  goto error;
242  }
243 
244  if (!(I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL)) { // verify if in master mode
245  goto error;
246  }
247 
248  // select slave
249  i2c_send_7bit_address(I2C(I2C_MASTER_I2C), slave, I2C_WRITE); // select slave
250  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
251  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
252  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
253  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_ADDR) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until address is transmitted
254  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
255  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
256  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
257  goto error;
258  }
259  if (!((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_TRA))) { // verify we are in transmit mode (and read SR2 to clear ADDR)
260  goto error;
261  }
262 
263  // send address
264  for (size_t i=0; i<address_size; i++) {
265  i2c_send_data(I2C(I2C_MASTER_I2C), address[i]); // send memory address we want to read
266  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
267  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
268  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
269  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
270  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
271  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
272  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
273  goto error;
274  }
275  }
276 
277  // write data
278  for (size_t i=0; i<data_size; i++) { // write bytes
279  i2c_send_data(I2C(I2C_MASTER_I2C), data[i]); // send byte to be written in memory
280  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
281  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
282  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
283  while (!(I2C_SR1(I2C(I2C_MASTER_I2C)) & I2C_SR1_TxE) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until byte has been transmitted
284  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
285  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
286  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
287  goto error;
288  }
289  }
290  to_return = true;
291 
292 error:
293  i2c_send_stop(I2C(I2C_MASTER_I2C)); // send stop to release bus
294  timer_set_counter(TIM(I2C_MASTER_TIMER),0); // restart timer
295  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
296  timer_enable_counter(TIM(I2C_MASTER_TIMER)); // enable timer for timeouts
297  while ((I2C_SR2(I2C(I2C_MASTER_I2C)) & I2C_SR2_MSL) && !timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)); // wait until bus released (non master mode)
298  timer_disable_counter(TIM(I2C_MASTER_TIMER)); // disable timer for timeouts
299  if (timer_get_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF)) { // timeout occurred
300  timer_clear_flag(TIM(I2C_MASTER_TIMER), TIM_SR_UIF); // clear flag
301  }
302  return to_return;
303 }
#define I2C_SCL_PORT(x)
get I2C port for SCL pin based on I2C identifier
Definition: global.h:208
library to communicate using I2C as master (API)
#define I2C(x)
get I2C based on I2C identifier
Definition: global.h:196
#define I2C_SDA_PIN(x)
get I2C port for SDA pin based on I2C identifier
Definition: global.h:214
global definitions and methods (API)
#define I2C_SDA_PORT(x)
get I2C port for SDA pin based on I2C identifier
Definition: global.h:210
#define RCC_TIM(x)
get RCC for timer based on TIM identifier
Definition: global.h:45
bool i2c_master_read(uint8_t slave, const uint8_t *address, size_t address_size, uint8_t *data, size_t data_size)
read from I2C slave
Definition: i2c_master.c:97
#define I2C_SCL_PIN(x)
get I2C pin for SCL pin based on I2C identifier
Definition: global.h:212
#define I2C_MASTER_I2C
I2C peripheral.
Definition: i2c_master.c:39
#define RCC_I2C_SCL_PORT(x)
get RCC for GPIO port for SCL based on I2C identifier
Definition: global.h:200
#define I2C_MASTER_TIMEOUT
timeout factor (compared to expected time)
Definition: i2c_master.c:46
#define I2C_MASTER_TIMER
timer peripheral
Definition: i2c_master.c:45
#define TIM(x)
get TIM based on TIM identifier
Definition: global.h:43
bool i2c_master_write(uint8_t slave, const uint8_t *address, size_t address_size, const uint8_t *data, size_t data_size)
write to I2C slave
Definition: i2c_master.c:216
#define RCC_I2C(x)
get RCC for I2C based on I2C identifier
Definition: global.h:198