dump_spi_flash
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| Both sides previous revisionPrevious revisionNext revision | Previous revisionNext revisionBoth sides next revision | ||
| dump_spi_flash [2021/04/15 11:06] – [J-Link] kingkevin | dump_spi_flash [2021/04/15 11:24] – [electrical] kingkevin | ||
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| This allows to customize the programmer to your needs and setup (regarding voltage level, clock speed, nRST pin of flash and MCU, ...). | This allows to customize the programmer to your needs and setup (regarding voltage level, clock speed, nRST pin of flash and MCU, ...). | ||
| - | ===== electrical ===== | + | ===== electrical |
| The most important part is using the right voltage so you don't damage the target chip or board. | The most important part is using the right voltage so you don't damage the target chip or board. | ||
| Line 243: | Line 243: | ||
| Connect the target voltage and your MCU voltage on each side, and the job is done. | Connect the target voltage and your MCU voltage on each side, and the job is done. | ||
| - | ===== interface ===== | + | ===== data interface ===== |
| The most common lines are the following: | The most common lines are the following: | ||
| Line 251: | Line 251: | ||
| * nWP: active low write protect. Set it low if you only intend to read out the flash and don't want to accidentally erase data. Set it high if you want to write it | * nWP: active low write protect. Set it low if you only intend to read out the flash and don't want to accidentally erase data. Set it high if you want to write it | ||
| * CLK: clock line with clock polarity: idle low, and clock phase: sample data on rising edge. Since SPI is a synchronous protocol, the data traffic is synchronized to this clock, provided by the master (your programmer). This allows you to set the frequency: very low for more reliable traffic (there is not lower limit), or very high for fast transfer (often up to 100 MHz). The clock also does not need to be periodic (allowing sloppy big-banging implementation) and the edge time not strict (allowing any voltage shifter technology) | * CLK: clock line with clock polarity: idle low, and clock phase: sample data on rising edge. Since SPI is a synchronous protocol, the data traffic is synchronized to this clock, provided by the master (your programmer). This allows you to set the frequency: very low for more reliable traffic (there is not lower limit), or very high for fast transfer (often up to 100 MHz). The clock also does not need to be periodic (allowing sloppy big-banging implementation) and the edge time not strict (allowing any voltage shifter technology) | ||
| + | * nCS: chip select line, active low. You must set it low to start a new transaction. It also allows to have multiple flash chips (SPI slaves) on the same data lines (you then just select the one you want to talk too) | ||
| * MOSI/DI: master output slave input (flash chip data input). You will send the commands on this pin | * MOSI/DI: master output slave input (flash chip data input). You will send the commands on this pin | ||
| * MISO/DO: master input slave output (flash chip data output). You will receive the replies and data on this pin | * MISO/DO: master input slave output (flash chip data output). You will receive the replies and data on this pin | ||
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| * in theory the data lines need to be driven as push-pull, but you can also drive them as open-drain (allowing using level shifter as the BSS138-based ones). But be aware that the chip will drive DO (and other lines in dual/quad mode) as push-pull | * in theory the data lines need to be driven as push-pull, but you can also drive them as open-drain (allowing using level shifter as the BSS138-based ones). But be aware that the chip will drive DO (and other lines in dual/quad mode) as push-pull | ||
| * each setup is different, and you have to find things out by yourself. Just don't forget to read the appropriate data sheet | * each setup is different, and you have to find things out by yourself. Just don't forget to read the appropriate data sheet | ||
| + | |||
| + | ===== instruction interface ===== | ||
| + | |||
| + | The instructions are sent in 8-bit packets, most significant bit first. | ||
| + | There are a couples of instructions common to most SPI flash chips, which allow you to perform basic operations: | ||
| + | |||
| + | * 0x9F, JEDEC ID: you will then read 3 bytes allowing you to identify the chip (manufacturer, | ||
| + | * 0x03, Read Data: followed by 3 bytes of data where you specify the start address of the data you want to read. After that you can read out as much data as you want | ||
dump_spi_flash.txt · Last modified: 2024/01/07 17:49 by 127.0.0.1
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