jtag
Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revisionNext revisionBoth sides next revision | ||
jtag [2020/01/22 10:49] – [mini ST-LINK V2] update board pictures kingkevin | jtag [2021/04/29 10:52] – [DISTORTEC JTAG-lock-pick Tiny 2] kingkevin | ||
---|---|---|---|
Line 151: | Line 151: | ||
{{: | {{: | ||
- | Instead on an STM32F103, this dongle uses a [[http:// | + | Instead on an STM32F103, this dongle uses a [[http:// |
I've seen pin compatible alternatives (ST STM8S003 vs Nuvoton N76E003), even architecture compatible (ST STM32F103 vs GigeDevice GD32F103), but they always had some differences (architecture, | I've seen pin compatible alternatives (ST STM8S003 vs Nuvoton N76E003), even architecture compatible (ST STM32F103 vs GigeDevice GD32F103), but they always had some differences (architecture, | ||
The CS32F103 seems like a complete clone of the STM32F103 (exact same pinout, architecture, | The CS32F103 seems like a complete clone of the STM32F103 (exact same pinout, architecture, | ||
Line 158: | Line 158: | ||
To check if this is a complete clone you could decapsulate the chip and compare the silicon die, or check the errata behaviour (I can't imagine they re-implemented it themselves, up to the mistakes). | To check if this is a complete clone you could decapsulate the chip and compare the silicon die, or check the errata behaviour (I can't imagine they re-implemented it themselves, up to the mistakes). | ||
The next step would be to have a CS32F103 chip in a package marked as STM32F103. | The next step would be to have a CS32F103 chip in a package marked as STM32F103. | ||
+ | |||
+ | == GC == | ||
+ | |||
+ | {{: | ||
+ | {{: | ||
+ | {{: | ||
+ | |||
+ | Most ST-LINK minis which I get now use the CKS32 chip. | ||
+ | I'm a bit sad because the CS32F103C8 really only has the advertised 64 KB of flash, while the STM32F103C8 actually has 128 KB (e.g. what the STM32F103CB has), and when you have a lot of debugging strings in your firmware, you very soon reach the limit of the 64 KB. | ||
+ | Thus, on my quest to find ST-LINK minis with STM32F103 (e.g. where the ground pin is not between SWDIO and SWCLK) I landed on this one. | ||
+ | Sadly it also does not use a STM32F103, but a STM32GC102C8. | ||
+ | I have no idea what this chip is. | ||
+ | The GC series does not exist (at least ST doesn' | ||
+ | I'm not sure if this was to save cost, because this is the first board I see with 2 ESD protections (one for USB, the other for SWDIO/SWCLK in addition to the inline protection resistors, and none for RST/SWIM). | ||
+ | |||
==== Baite ==== | ==== Baite ==== | ||
Line 370: | Line 385: | ||
==== PIC USB-Blaster ==== | ==== PIC USB-Blaster ==== | ||
- | This one uses a Microchip PIC18F14 micro-controller and has no buffer (thus only supporting | + | This one uses a Microchip PIC18F14 micro-controller |
{{: | {{: | ||
Line 398: | Line 413: | ||
But v8 and v9 are not supported anymore by J-Link, meaning no new feature will be added to them. | But v8 and v9 are not supported anymore by J-Link, meaning no new feature will be added to them. | ||
Instead I recommend to get the [[https:// | Instead I recommend to get the [[https:// | ||
+ | |||
+ | Here pictures from devices not from official distributors, | ||
They come in the same case: | They come in the same case: | ||
Line 421: | Line 438: | ||
Here a J-Link v10. | Here a J-Link v10. | ||
- | This is currently the only version being developed on. | ||
It uses a NXP LPC4337 which supports USB high speed, and allows faster debugging speeds. | It uses a NXP LPC4337 which supports USB high speed, and allows faster debugging speeds. | ||
In addition to the others, it adds cJTAG support: | In addition to the others, it adds cJTAG support: | ||
Line 427: | Line 443: | ||
{{: | {{: | ||
{{: | {{: | ||
+ | |||
+ | Here a [[https:// | ||
+ | It is supposed to be embedded on development board and provide an easy way to flash the main micro-controller. | ||
+ | It have much less capabilities (no JTAG, only SWD, ...) and less protections, | ||
+ | Additionally it provides a UART interface, ideal for printf debugging. | ||
+ | I actually can be implemented on several micro-controller, | ||
+ | |||
+ | {{: | ||
+ | {{: | ||
+ | |||
+ | |||
===== Texas Instruments XDS100v3 ===== | ===== Texas Instruments XDS100v3 ===== | ||
Line 439: | Line 466: | ||
===== DISTORTEC JTAG-lock-pick Tiny 2 ===== | ===== DISTORTEC JTAG-lock-pick Tiny 2 ===== | ||
- | The [[http:// | + | The [[http:// |
{{: | {{: |
jtag.txt · Last modified: 2024/01/07 17:49 by 127.0.0.1