Differences

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--- jtag [2016/01/12 15:26] – created kingkevin
+++ jtag [2016/02/03 13:47] – [ST-Link v2 (clone)] add pinout kingkevin
@@ Line 24: / Line 24: @@
 {{:jtag:dsc02406.jpg?0x100|pinout sticker}}
 {{:jtag:st-link_v2_baite.svg?0x100|pinout}}
+^ STM32F103C8 signal ^ STM32F103C8 pin ^ adapter pin ^ adapter signal ^
+| PA7 | 17 | 1 | JRST |
+| AMS1117 |  | 2 | 3V3 |
+| USB VCC |  | 3 | 5V |
+| PA4 | 14 | 4 | JTCK/SWCLK |
+| PB11 | 22 | 5 | SWIM/SWDIO |
+| PA14 | 37 | 6 | JTMS |
+| USB GND |  | 7 | GND |
+| PA5 | 15 | 8 | JTDO |
+| PB6 | 42 | 9 | SWIM_RST |
+| PA6  | 16 | 10 | JTDI |
+| PB12,PB14 | 25,27 |  |  100 ohms |
+| PB5 | 41 |  | LED |
+the adapter pins are protected with a 220 ohms resistor.
   * one [[http://www.aliexpress.com/item/Hot-Sale-1PCS-ST-LINK-Stlink-ST-Link-V2-Mini-STM8-STM32-Simulator-Download-Programmer-Programming/32343514985.html|more generic]]
 {{:jtag:dsc02407.jpg?0x100|device front}}
@@ Line 33: / Line 50: @@
 This is newer variant of JTAG which requires only 2 signal lines instead of 4+.
 But but aware, they both have different pinouts on the connector.
+The second one offers 2 more power ports at the expense of JTAG TDI and TDO/SWO.
-These JTAG adapter are based STM32F1xx ARM Cortex M3 micro-controllers.
+These JTAG adapters are based STM32F1xx ARM Cortex M3 micro-controllers.
 And ironically enough I in turn use them to program and debug STM32F1xx ARM Cortex M3 micro-controllers.
@@ Line 132: / Line 150: @@
 Debug: 389 846 pld.c:207 handle_pld_init_command(): Initializing PLDs...
 </code>
+Now you can also use it, here with an STM32F1 micro-controller:
+<code bash>
+openocd --file interface/altera-usb-blaster.cfg --file target/stm32f1x.cfg
+Open On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-16:26)
+Licensed under GNU GPL v2
+For bug reports, read
+	http://openocd.org/doc/doxygen/bugs.html
+Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only
+Info : only one transport option; autoselect 'jtag'
+adapter speed: 1000 kHz
+adapter_nsrst_delay: 100
+jtag_ntrst_delay: 100
+none separate
+cortex_m reset_config sysresetreq
+Info : No lowlevel driver configured, will try them all
+Info : usb blaster interface using libftdi
+Error: unable to get latency timer
+Info : This adapter doesn't support configurable speed
+Info : JTAG tap: stm32f1x.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
+Info : JTAG tap: stm32f1x.bs tap/device found: 0x16410041 (mfg: 0x020, part: 0x6410, ver: 0x1)
+Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
+</code>
+==== SEGGER J-Link (clone) ====
+The [[http://www.aliexpress.com/item/FREE-SHIPPING-V8-ARM-Emulator-supports-ARM7-ARM9-ARM11-Cortex-M3-core-ADS-IAR-STM32-Emulator/32262570128.html|O-Link-ARM V8]] is a [[https://www.segger.com/jlink_base.html|SEGGER J-Link]] clone.
+{{:jtag:imag0403.jpg?0x150|device front}}
+{{:jtag:imag0404.jpg?0x150|device back}}
+{{:jtag:imag0406.jpg?0x150|PCB front}}
+It supports JTAG, SWD, SWO, RTCK, and voltage reference.
+That makes it the most complete JTAG adapter I have.
 ===== tricks =====
@@ Line 144: / Line 197: @@
 Thus it sometimes is useful to just list the TAPs available on a chain to know which devices are present.
-This is easily done with urJTAG:
+This is easily done with urJTAG (here with the USB Blaster):
 <code bash>
 jtag
@@ Line 172: / Line 225: @@
 OpenOCD also scans the chain if no target is provided (the adapter still need to be defined):
 <code bash>
-openocd --file interface/altera-usb-blaster.cfg --file target/stm32f1x.cfgOpen On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-11:18)
+openocd --file interface/altera-usb-blaster.cfg
+Open On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-16:26)
 Licensed under GNU GPL v2
 For bug reports, read
@@ Line 178: / Line 233: @@
 Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only
 Info : only one transport option; autoselect 'jtag'
-adapter speed: 1000 kHz
-adapter_nsrst_delay: 100
-jtag_ntrst_delay: 100
-none separate
-cortex_m reset_config sysresetreq
 Info : No lowlevel driver configured, will try them all
 Info : usb blaster interface using libftdi
 Error: unable to get latency timer
 Info : This adapter doesn't support configurable speed
-Info : JTAG tap: stm32f1x.cpu tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
+Warn : There are no enabled taps.  AUTO PROBING MIGHT NOT WORK!!
-Info : JTAG tap: stm32f1x.bs tap/device found: 0x16410041 (mfg: 0x020, part: 0x6410, ver: 0x1)
+Info : JTAG tap: auto0.tap tap/device found: 0x3ba00477 (mfg: 0x23b, part: 0xba00, ver: 0x3)
-Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
+Info : JTAG tap: auto1.tap tap/device found: 0x16410041 (mfg: 0x020, part: 0x6410, ver: 0x1)
+Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 4 -expected-id 0x3ba00477"
+Warn : AUTO auto1.tap - use "jtag newtap auto1 tap -irlen 5 -expected-id 0x16410041"
+Warn : gdb services need one or more targets defined
+</code>
+''0x3ba00477'' corresponds to the Cortex-M3 TAP, and ''0x16410041'' to the boundary scan TAP, as documented in the [[http://www.st.com/web/en/resource/technical/document/reference_manual/CD00171190.pdf|STM32F1xx reference manual]].
+While the ST-Link v2 is mainly meant to be used as SWD adapter, it also supports JTAG. Both are implemented with the High Level Adapter (HLA) driver. But it seems scan chain is [[http://sourceforge.net/p/openocd/mailman/message/31038247/|not supported by the HLA]].
+<code bash>
+openocd --file interface/stlink-v2.cfg -c "transport select hla_jtag" -c "adapter_khz 100"
+Open On-Chip Debugger 0.10.0-dev-00189-g554313b (2016-01-12-16:26)
+Licensed under GNU GPL v2
+For bug reports, read
+	http://openocd.org/doc/doxygen/bugs.html
+hla_jtag
+adapter speed: 100 kHz
+Info : clock speed 100 kHz
+Error: BUG: current_target out of bounds
 </code>